Silicon Design Engineering Sr Manager

Lead the global PCIe / CXL Center of Excellent (CoE) team on developing latest state of the art PCIe / CXL solution for next generation FPGA in the latest process technology node. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards to ensure key factors such as power, performance, area, and cost are meeting requirements. Provide leadership in PCIe and CXL protocol, including transaction layers, data link layers, and physical layers. Drive innovation in design methodologies, techniques, and tools to improve performance, power efficiency, and latency. Collaborate with cross-functional teams including hardware, software, and verification teams to ensure integrated and optimized PCIe designs for driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Job Description :

Lead the global PCIe / CXL Center of Excellent (CoE) team on developing latest state of the art PCIe / CXL solution for next generation FPGA in the latest process technology node. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards to ensure key factors such as power, performance, area, and cost are meeting requirements. Provide leadership in PCIe and CXL protocol, including transaction layers, data link layers, and physical layers. Drive innovation in design methodologies, techniques, and tools to improve performance, power efficiency, and latency. Collaborate with cross-functional teams including hardware, software, and verification teams to ensure integrated and optimized PCIe designs for driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications :

Bachelor’s or Master's degree in electrical / computer engineering or related field and 10+ years of experience. Experience in managing design technical team in delivering IP / SS logic / RTL design from uArchitecture to physical implementation, with experience on industry EDA tool such as LINT, CDC, PT-STA, Fishtail, Power UPF etc Good knowledge of PCIe / CXL or high-speed serial interface protocol, such as USB or Ethernet. Knowledge on FPGA background would be a plus. Highly motivated individual, self starter with strong leadership & team player with good communication skill. Job Type :

Regular Shift :

Shift 1 (Malaysia) Primary Location :

Penang 15 Additional Locations :

Posting Statement :

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Seniority level :

Director Employment type :

Full-time Job function :

Engineering and Information Technology Industries :

Semiconductor Manufacturing

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