Responsibilities
- Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database ready for manufacturing.
- Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power / clock distribution, reliability, and power and noise analysis.
- Perform verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
- Analyze results and make recommendations to fix violations for current and future product architecture.
- Apply design optimization knowledge to improve product-level parameters such as power, frequency, and area. Participate in the development and improvement of physical design methodologies and flow automation.
- Possess expertise in PCIe or other I / O protocol SIP logic partition physical planning and design.
Education Requirements
Education : Bachelor’s degree in computer engineering, electronic engineering, or related field.
Minimum Qualifications
5+ years of relevant experience in physical design engineering, with multiple tape‑out experience in deep sub‑micron process nodes.In‑depth, extensive knowledge and hands‑on experience in physical design flow and relevant EDA tools.In‑depth, extensive knowledge and hands‑on experience in physical design signoff flow (STA, LEC, ERC, DRC).Hands‑on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages VHDL and Verilog.Experience mentoring junior team members and charting their development for success.Strong initiative, analytical / problem‑solving skills, teamwork, multitasking, and ability to work within a diverse team environment.Preferred Requirements
Bachelor’s or master’s degree in computer engineering, electronic engineering, or related field.5+ years of experience in physical design involving multiple clock domains, clock and power management.Low‑power design, tools and methodologies, power intent UPF specifications.Job Details
Job Type : Regular
Shift : Shift 1 (Malaysia)
Primary Location : Penang 15, Penang, Malaysia
Equal Employment Opportunity Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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