Design Verification Engineer

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Who we are :

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at

We are seeking a skilled and experienced Design Verification Engineer to join our dynamic team in Penang, Malaysia. The ideal candidate will play a pivotal role in ensuring the functional correctness, power efficiency, and protocol compliance of our cutting-edge semiconductor designs. This position is suited for individuals with a strong technical background in advanced verification methodologies and protocols.

Experience : 4+ years

Key Responsibilities :

• Develop and implement constrained-random verification environments using SystemVerilog and UVM .
• Write and execute test plans , testcases , scoreboards , monitors , and coverage models.
• Debug and analyze test failures to identify RTL or testbench issues.
• Collaborate closely with RTL designers, architecture, and firmware teams to ensure design correctness and coverage closure.
• Develop reusable verification components and contribute to the improvement of the verification infrastructure and methodology.
• Analyze functional and code coverage metrics; drive coverage closure.
• Participate in design and verification reviews and provide feedback on specifications and testability.

Required Qualifications :

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