Senior Design Engineer

Part of the global PCIe / CXL Center of Excellence (CoE) team, developing the latest & state-of-the-art PCIe / CXL solutions for next-generation FPGA in the latest process technology node.

Responsibilities :

• Develop logic / RTL design and simulation for IP / SoC design & integrate logic of IP blocks and subsystems into a full chip SoC or discrete component design.
• Participate in defining PCIe / CXL architecture and microarchitecture features; collaborate with IP providers to integrate and validate IPs at the SoC level.
• Lead power management for the PCIe subsystem, working with PD owners on timing convergence.
• Apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals, ensuring design integrity for physical implementation.
• Review verification plans and implementations; resolve RTL test failures to ensure feature correctness.
• Conduct quality checks across logic design aspects, from RTL to timing / power convergence; drive quality assurance for smooth IP / SoC handoff.

Qualifications :

Additional Details :

About Altera :

Altera, an Intel Company, provides leadership in programmable solutions from cloud to edge, including FPGAs, CPLDs, IP, tools, and more, fostering innovation and shaping the future of technology.

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