SkyeChip is pushing the boundaries of semiconductor innovation. Our team is growing, and we’re looking for a Senior Design Verification Engineer / Technical Lead to help shape the next generation of NoC IP solutions.
Responsibilities :
- Architect and lead scalable UVM-based testbenches for high-performance, high configurable NoC IP designs
- Define and drive DV strategy, methodology, and AI-assisted verification improvements
- Own test plans, coverage closure, and protocol verification
- Collaborate closely with architecture, RTL, and software teams to deliver high-quality IP
- Mentor and guide junior and mid-level engineers
Requirements :
5–20 years of DV experience, ideally with NoC interconnect and bus protocols (e.g. AXI / AXI-Lite / AHB / APB)Strong expertise in SystemVerilog, UVM, scripting, functional coverage, and scoreboardingHands-on skills in debug, testbench development, regression, simulation (VCS, Xcelium), and combined coverage (functional, code, parameter, topology) closureA passion for innovation and solving complex verification challengesWe offer a collaborative, innovative environment with exposure to advanced verification methodologies, competitive compensation, career growth, and real influence on methodology direction.
SkyeChip is an equal opportunities employer and welcomes applications from all qualified candidates.
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