We are seeking a Front End Integration Engineer to perform IP level FEInt tasks.
The ideal candidate will have expertise in synthesis, linting, CDC (clock domain crossing), LEC (logical equivalence checking), UPF (Unified Power Format), and other relevant areas.
Responsibilities
- Conduct synthesis and optimization of IP blocks
- Perform linting to ensure code quality and adherence to design guidelines
- Conduct CDC analysis to identify and address potential issues in clock domains
- Perform LEC to ensure design consistency before and after synthesis
- Implement UPF for power management in the design
Qualifications
Willing to relocate to PenangBachelor's degree in Electrical Engineering, Computer Engineering, or related fieldAt least 2 years of experience in front end integration tasksStrong expertise in synthesis, linting, CDC, LEC, and UPFProficient in industry standard EDA toolsRich verification experience (block or SoC level, simulation, formal verification is an additional advantage)Strong UVM, System Verilog, C++, Perl, Python knowledgeFamiliar with Standard AMBA / AXI / AHB interface protocolStrong problem-solving, analytical skills, good communication and teamwork skills#J-18808-Ljbffr