Hiring Top Semiconductor Engineers across APAC Region and Vietnam | Connecting Talents to Opportunities | Talents Strategist | Follow me for more Job…
Job Summary
Experience : 3-8 years
We are seeking a talented Design Verification (DV) Engineer with hands‑on experience in USB (2.0 / 3.x / Type-C / PD) protocol verification. The candidate will be responsible for developing and executing verification plans, creating testbenches, writing and debugging test cases, and ensuring high‑quality silicon delivery.
Key Responsibilities
- Develop and implement comprehensive verification plans for USB IP and subsystem designs.
- Create SystemVerilog / UVM‑based testbenches and reusable verification components.
- Write directed and random tests, perform coverage analysis, and close coverage metrics.
- Debug complex design and testbench issues using simulation and waveform analysis tools.
- Work closely with design, architecture, and validation teams to ensure design functionality and performance.
- Participate in reviews for test plans, testbench architecture, and verification results.
- Integrate USB IP into SoC environments and verify system‑level functionality.
Required Skills & Experience
Bachelor’s or Master’s degree in Electrical / Electronics / Computer Engineering or related field.3+ years of experience in ASIC / FPGA design verification .Strong expertise in SystemVerilog , UVM , and functional coverage methodologies.Hands‑on experience verifying USB 2.0 / 3.0 / 3.1 / Type‑C / PD protocols.Solid understanding of AXI / AHB / APB interconnects and SoC integration flows.Proficiency with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa, etc.).Strong debugging skills and familiarity with waveform analysis tools.Excellent communication and problem‑solving abilities.Preferred Qualifications
Experience with USB certification or post‑silicon validation .Knowledge of C / C++ for testbench modeling or embedded software interaction.Familiarity with Python or Perl scripting for automation.Exposure to PCIe, DDR, or other high‑speed interfaces is a plus.Contact
Anna - WhatsApp - Email :
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Engineering Services and Semiconductor Manufacturing
#J-18808-Ljbffr