Principal Engineer Digital Physical Design

We are searching for a Technical Leader and future Team Manager with focus on building up an own team. Job Description

In your new role you will :

• All aspects of RTL2GDS physical implementation for block or full chip level as Technical Lead and future Team Manager for a growing digital physical implementation team.
• Working alongside with own team and other functional teams and different development sites to ensure on time delivery and high-quality results.
• Possess strong hands-on working knowledge of deep sub-micron ASIC implementation.
• Wide experience with industry standard EDA tools for digital implementation and signoff (Synopsys DC / ICC / ICC2 / PrimeTime, Cadence RC / Genus / Innovus / Tempus)
• Proven responsibility for full design flow from constraints write up to design closure and tapeoutFloor planning and power planning.Placement, Clock tree synthesis, routingDesign optimization, layout verification, and timing closure.Solid team player.Proactive and highly self -driven.Proven problem solving, debug and organisational skills.Experience with TCL / PERL scripting and flow automation to improve flow QoR and reduce TAT.
• Preferred Skills and Qualifications
• RTL Synthesis and Implementation
• Logical equivalence
• Static timing analysis
• Low power design implementation
• Power analysis and IR drop signoff
• Layout verification
• Leading as Team Manager

Your Profile

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