Staff Engineer Digital Physical Design

In your new role you will :

• All aspects of RTL to GDS physical implementation for block or full chip level.
• Working alongside with other team members to ensure on time delivery and high-quality results.
• Possess strong hands-on working knowledge of deep sub-micron ASIC implementation.
• Wide experience with industry standard EDA tools for digital implementation and signoff (Synopsys DC / ICC / ICC2 / Prime Time, Cadence RC / Genus / Innovus / Tempus)
• Proven responsibility for full design flow through to design closure and tape out
• Floor planning and power planning.
• Clock tree synthesis.
• Design optimisation and timing closure.

Your Profile

You are best equipped for this task if you have :

• Solid team player.
• Proactive and self-starter.
• Proven problem solving, debug and organisational skills.
• Experience with scripting and flow automation to improve flow QoR andreduce TAT.
• Preferred Skills : -RTL Synthesis.Logical equivalence.Static timing analysis.Low power design implementation.Power analysis and IR drop signoff