IC Physical Layout Design Engineer

Description Responsible for VLSI component physical layout and data entry, translating schematic into layout geometry at cell / fub / floor planning / module level. Perform physical assembly and layout verification. Use of CAD tools such as Cadence PLE / VXL(Virtuoso-XL) and layout verification tools extensively. Preparation of multi dimensional layout and detailed drawing of semiconductor devices. Built optimize layout, perform ECO changes within broadly defined physical parameters. Troubleshooting in layout verification LVS, DRC and others errors like Antenna for fixes within specific project timeline. (Calibre Standard). Exposure to the most advance Mask / Layout design software tools and hardware technologies (< 22nm). Qualification Candidate must possess at least a Bachelor's Degree Engineering (Computer / Telecommunication), Engineering (Electrical / Electronic) or equivalent. Required skill(s) : VLSI (Very Large Scale Integration), PLE (Physical Layout Estimation), ECO (Engineering Change Orders). Preferred skill(s) : LVS (Layout vs Schematic), DRC (Design Rule Check), Calibre.