Position Overview :
We are looking for a skilled FPGA Engineer to join our dynamic team. The ideal candidate will have a strong background in HDL design, FPGA development tools, and digital logic design, as well as a passion for creating innovative solutions. You will be responsible for developing and testing FPGA designs, integrating open-source soft IP cores, and ensuring system reliability through rigorous debugging and optimization.
Key Responsibilities :
- Design, develop, and verify FPGA-based systems using HDLs such as Verilog, SystemVerilog, or VHDL.
- Work with development tools like Xilinx Vivado, Lattice Diamond / Radiant, and OpenFPGA for synthesis, simulation, and implementation.
- Test and validate the correctness of RTL designs.
- Stitch open-source soft IP cores (e.g., RISC-V cores like VexRiscv) with other hardware IPs.
- Develop and debug FPGA designs using interfaces such as AXI, Wishbone, Ethernet, I2C, SPI, and UART.
- Perform timing analysis and place-and-route tasks to meet design constraints.
- Debug and optimize hardware designs in real-time using tools like ChipScope / ILA, SignalTap, and logic analyzers.
- Collaborate with cross-functional teams to define project requirements and deliverables.
Required Skills and Expertise :
HDL Proficiency :
Strong knowledge of Verilog, SystemVerilog, and / or VHDL for RTL design.Familiarity with high-level HDLs like Spinal HDL, Chisel, or Bluespec SystemVerilog.FPGA Development Tools :
Hands-on experience with Xilinx Vivado, Intel Quartus Prime, and Lattice Diamond / Radiant.Proficiency in simulation tools such as ModelSim, QuestaSim, or Verilator for debugging and verification.Synthesis and Implementation :
Knowledge of synthesis and timing analysis, including setup and hold timing, to ensure reliable designs.Familiarity with place-and-route tools like Vivado P&R or Quartus Fitter.Hardware Debugging :
Hands-on experience with logic analyzers, oscilloscopes, and FPGA-specific tools like ChipScope / ILA or SignalTap.Ability to debug and optimize hardware designs in real-time.Digital Design Fundamentals :
Strong understanding of combinational and sequential circuits, finite state machines, and pipelining.Familiarity with concepts like clock domain crossing, low-power design, and latency optimization.What You Will Be Working On :
Testing and validating the correctness of RTL codes.Integrating open-source soft IP cores with various other IPs to create cohesive systems.Nice to Have :
A portfolio showcasing previous FPGA projects and designs.Contributions to open-source FPGA or hardware projects.Familiarity with open-source toolchains like SymbiFlow and Yosys.What We Offer :
Opportunity to work on cutting-edge FPGA projects.A collaborative and innovative work environment.Continuous learning and growth opportunities.Flexible work arrangements and competitive compensation.