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Lead RTL Engineer
USTPenangMalaysia, Penang, Malaysia8 hours ago
Job descriptionBachelor’s / Master’s in EE or related field. 8+ years’ experience in RTL design and front-end ASIC implementation. Proficient in Verilog, synthesis, timing, and low-power methodologies. Familiar with EDA tools (Design Compiler, PrimeTime, Conformal, VC-Static, Formality). Skilled in Unix / Linux and scripting (TCL, Perl, Python). Good communication and problem-solving skills. Mid-Senior level Full-time IT Services and IT Consulting
Overview
Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies
Responsibilities
- Develop and implement RTL for large digital ASIC / SoC projects.
- Perform synthesis, CDC / lint, timing closure, LEC, and UPF low-power design.
- Collaborate with architecture, verification, and physical design teams to meet project goals.
- Ensure RTL quality through reviews, simulations, and static checks.
Requirements
Seniority level
Employment type
Job function
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Lead Engineer • PenangMalaysia, Penang, Malaysia
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