Senior SoC Integration / Signoff Engineer

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Overview

Senior SoC Integration / Signoff Engineer responsible for physical design, verification, and signoff across SoC and custom IPs, from RTL to GDSII, to create a manufacturable design database.

Responsibilities

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power / clock distribution, reliability, and power and noise analysis
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking
• Analyzes results and makes recommendations to fix violations for current and future product architecture
• Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation
• Possesses hands on expertise in various process nodes full chip physical integration, system level place and route and system level verification signoff

Qualifications

Education Requirements

Bachelor's degree in computer engineering, electronic Engineering or related field.

Minimum Qualifications

Preferred Requirements

Job Details

Other

Posting Statement : All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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