Design Verification Engineer

Design Verification Engineer – UST

We are seeking a motivated and detail-oriented Design Verification Engineer to join our team. The ideal candidate will have hands-on experience in System Verilog and UVM, along with a solid understanding of verification methodologies and testbench development.

Key Responsibilities

• Develop, implement, and maintain UVM-based testbenches for block-level and system-level verification.
• Create and execute test plans, write test cases, and analyze simulation results.
• Debug RTL and testbench issues using waveform analysis and simulation tools.
• Collaborate closely with design, architecture, and validation teams to ensure comprehensive functional coverage.
• Contribute to continuous improvement of verification methodology and automation.

Required Skills and Qualifications

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