Job Description
In your new role you will :
- Participate in block / IP / chip floor planning from scratch, performing routing & layout verification (such as LVS, DRC, Antenna & others) and troubleshooting the results.
- Co-lead / lead the physical layout of IP / full chip design by working closely with cross-functional team leaders.
- Conduct thorough layout design reviews internally & external review with circuit designers.
- Use CAD tools extensively (Cadence Virtuoso VXL & Mentor Calibre) in IP / chip integration and verification.
- Guide and coach junior engineers to ensure on-time delivery & quality.
Your Profile
You are best equipped for this task if you have :
Bachelor’s Degree in Electrical / Electronic Engineering / Physics with VLSI exposure or equivalent, with 9 to 14 years of experience in layout design preferred.Hands-on experience in analog layout from scratch, implementation of analog layout techniques, IR drop / EM analysis.Deep understanding of analog circuit layout concepts in submicron CMOS technologies.Strong technical, analytical, & problem-solving skills in layout design.Ability to work as a strong team player and participate in cross-functional activities.Good interpersonal, verbal, and communication skills, with good initiative at work.#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions for power systems and IoT, Infineon enables solutions for green energy, clean mobility, and smart IoT. We drive innovation and customer success, caring for our people and empowering them to reach ambitious goals. Join us in making life easier, safer, and greener.
Are you in?
We are committed to creating the best Infineon for everyone. We embrace diversity and inclusion, welcoming everyone for who they are. Our environment is based on trust, openness, respect, and tolerance, and we are dedicated to providing equal opportunities. Our recruiting decisions are based on experience and skills. Please inform your recruiter if you need accommodations during the interview process.
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