DFX Design Verification Engineer

Responsibilities

Understand DFx architecture and develop Pre-silicon DFx validation tests to verify design quality. Working knowledge of DFx ICL / PDL based verification Create test plans for RTL validation, define and run simulation models, find and implement corrective measures for failing RTL tests, including regression and debug tests, to ensure security coverage. Drives technical reviews of plans and proofs with design and architecture teams. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Deliver validated DFx IP / SoC for simulation and post silicon usage. Partner with post-Silicon Team to enable DFx test capability in silicon. Support debug of any test content failures including silicon diagnosis in the post-Silicon environment. Maintains and improves existing functional verification infrastructure and methodology. Qualifications

Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience. Hands-on experience in DFX / RTL Design / integration verification. Experience in scripting proficiency (perl, python, TCL, etc) to automate design process and improve efficiency. Ability to communicate well with counterparts and key stakeholders. Familiar with tools for simulation and debug such as VCS and Verdi. Good understanding on UVM, SV, assertions and coverage.

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