Senior Staff IP Logic Design / Microarchitect

The Senior IP Logic Design Engineer will be responsible for the design and implementation of logic design, microarchitecture definition, RTL coding, IP releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also include performance optimization and ensuring design functionality through verification and validation processes.

Key Responsibilities

• IP Design Responsibility

Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.

Ability to orchestrate the team on validation requirements to catch all possible boundary conditions of logic bugs.

Deep knowledge on Lint and CDC flow and ability to drive the Lint and CDC convergence.

#J-18808-Ljbffr