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Digital IC Design Engineer (Fresh Graduate – Masters / Ph.D)

Digital IC Design Engineer (Fresh Graduate – Masters / Ph.D)

NexperiaPenangMalaysia, Penang, Malaysia
2 hari lalu
Penerangan pekerjaan

Nexperia is a world‑class company in semiconductor development and in‑house production. A proven global player with an entrepreneurial mentality. At our core is an 13,000+ strong international network with a singular focus. Built on passion and commitment to our work, belief in our goals and a drive to succeed regardless of the challenges we face. We support, reward and challenge individuals equally, in a dynamic and energetic environment.

Nexperia is a world‑class company in semiconductor development and in‑house production. We form a global network of talent, with passion and performance, perseverance and professionalism. Join TeamNexperia and become part of a leading company that supports, rewards and challenges you equally, in a dynamic environment, working for world‑class results. Talk to us today and learn your true capabilities in an energetic company where you will develop and thrive, the Efficiency Company – Nexperia.

About The Role

As a Digital IC Design Engineer , you will work on the design and development of advanced digital circuits that form the foundation of Nexperia’s power management and signal processing solutions. You will gain hands‑on experience in RTL design, verification, synthesis, and optimization, collaborating closely with experienced engineers and mentors across our global design teams.

This is an excellent opportunity for fresh graduates with a Master’s or Ph.D. who are passionate about semiconductor design and eager to begin a career in the digital IC domain.

What You Will Do

  • Contribute to digital front‑end design for power management and signal processing IC products
  • Assist in defining and architecting digital systems based on product requirements
  • Develop RTL functional designs and perform verification using Verilog / SystemVerilog
  • Perform lint, clock domain crossing (CDC), and reset domain crossing (RDC) checks
  • Support timing constraint creation and analysis
  • Participate in synthesis, logic equivalence checks, and static timing analysis
  • Help optimize designs for performance, power, and area
  • Contribute to Design‑for‑Test (DFT) architecture and implementation
  • Develop automation scripts using Python or Perl
  • Prepare and maintain clear technical documentation

What You Will Need

  • Master’s or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline
  • Strong academic foundation in digital electronics, logic design, and computer architecture
  • Knowledge of Verilog or SystemVerilog RTL coding
  • Familiarity with simulation, synthesis, and timing analysis concepts
  • Enthusiasm to learn EDA tools such as Cadence or Synopsys
  • Strong analytical and problem‑solving skills
  • Good communication and teamwork abilities
  • A growth mindset and passion for innovation in semiconductor technology
  • Talent acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright © material and the word Nexperia® is a registered trademark.

    D&I Statement

    As an equal‑opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.

    In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women’s groups. Nexperia is committed to increasing women in management positions to 30% by 2030.

    #J-18808-Ljbffr

    Buat amaran kerja untuk carian ini

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