RTL Design Engineer

Overview

Who we are :

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at Experience :

6-8 years Education :

Bachelors or Masters degree in computer engineering / Electrical Engineering We are looking for a detail-oriented RTL Design Engineer to join our chip design team. The candidate will primarily be responsible for RTL coding based on provided specifications and microarchitecture. You will also collaborate with static verification engineers to ensure high-quality RTL and participate in RTL integration activities.

Responsibilities

Develop RTL code (Verilog / SystemVerilog) based on given specifications and microarchitecture documents. Ensure RTL quality by working closely with static verification resources for Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks. Participate in the integration of RTL modules, ensuring correct interfacing and functionality across the design. Collaborate with design, verification, and integration teams to support smooth design handoffs and early issue identification. Maintain coding standards and best practices to ensure readability, reusability, and maintainability of RTL code. Assist in debugging RTL issues uncovered during simulation, linting, or static verification. Support timing closure and power optimization by writing synthesizable and efficient RTL. Document RTL designs, integration notes, and verification reports.

Required Skills and Qualifications

Bachelor’s / Master’s degree in Electrical Engineering, Computer Engineering, or related field. Strong RTL coding skills in Verilog or SystemVerilog. Experience working from microarchitecture and specifications to RTL implementation. Familiarity with static verification tools and methodologies, including Lint, CDC, and RDC checks. Understanding of RTL integration flow and challenges. Good debugging skills and ability to work with simulation and static analysis tools. Knowledge of basic digital design principles, finite state machines, pipelining, and clock domain crossing. Effective communication and teamwork skills.

Preferred

Experience with version control tools (Git, SVN). Familiarity with verification methodologies like UVM is a plus. Exposure to ASIC or FPGA design flow. Scripting knowledge (Tcl, Python) to automate RTL tasks.

Contact

Ms. Anna - WhatsApp : Email :

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