PCIe / CXL Design Tech Lead

AlteraBayan Lepas, Penang, Malaysia

30+ hari lalu

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Part of the global PCIe / CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe / CXL solution for next generation FPGA in the latest process technology node.
Develops logic / RTL design and simulation for IP / SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Participates in the definition of PCIe / CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Performs quality checks in various logic design aspects ranging from RTL to timing / power convergence. Drives quality assurance compliance for smooth IP / SoC handoff.

Job Details

Job Description :

Part of the global PCIe / CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe / CXL solution for next generation FPGA in the latest process technology node.

Develops logic / RTL design and simulation for IP / SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

Participates in the definition of PCIe / CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level.

Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Performs quality checks in various logic design aspects ranging from RTL to timing / power convergence. Drives quality assurance compliance for smooth IP / SoC handoff.

Qualifications

Bachelor’s degree in electrical / computer engineering or related field and 7+ years of experience Or a master’s degree in electrical / computer engineering or related field and 6+ years of experience.

Experience in micro-architecture (clocking, reset, power, etc) definition & debug. Good knowledge of PCIe / CXL or high-speed serial interface protocol, such as USB or Ethernet.

5+ years of RTL coding and / or IP integration experience into SoC design. Experience in design related tools such as LINT, CDC, PT-STA, Fishtail, Power UPF etc & design concept such as data flow, algorithm state machine, finite state machines, and timing charts.

Knowledge on FPGA background would be a plus.

Highly motivated individual, team player with good communication skill.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location : Penang 15

Additional Locations :

Ecospace 1

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Design, Art / Creative, and Information Technology

Industries

Semiconductor Manufacturing

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Tech Lead • Bayan Lepas, Penang, Malaysia