Sr.DV、STA、DFT、PD、Validation Engineer

PenguinChip Sdn. Bhd.Bayan Lepas, Penang, Malaysia

5 hari lalu

Penerangan pekerjaan

Chip Design Recruitment Specialist

Competitive salary and bonus structure

Opportunities for professional growth and development

Collaborative and innovative work environment

Application Instructions :

Please submit your resume and cover letter to with the subject line “Name-Position Applied For”

Responsibilities

1. Candidate should be able to work independently on various DV task and providing technical guidance to DV team.
2. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
3. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
4. Estimate the time required to write the new feature tests and any required changes to the test environment.
5. Build the directed and random verification tests.
6. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
7. Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

Requirements

1. Proficient in IP / SoC level ASIC verification.

2. Proficient in debugging firmware and RTL code using simulation tools.

3. Proficient in using UVM testbenches and working in Linux and Windows environments.

4. Strong background with UVM, Verilog, System Verilog, C, and C++.

5. USB, UFS, Ethernet, PCIE, AXI knowledge is a plus.

6. Developing UVM based verification frameworks and testbenches, processes and flows.

7. Automating workflows in a distributed compute environment.

8. Exposure to power aware simulations is a plus.

9. Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)

10. Good working knowledge of SystemC and TLM with some related experience.

11. Scripting language experience : Perl, Ruby, Makefile, shell preferred.

12. Exposure to leadership or mentorship is an asset.

13. 3-15yrs of digital IP verification with SV / UVM / formal verification or new methodology of the industry.

Responsibilities

1. Do working assignment for team members, tracking and supporting for critical problems.

2. Co‑work with IP / DFT / PD team to improve timing / area / power during synthesize.

3. Netlist quality check including EQV / LowPower / Timing.

4. Generate full‑chip level SDC and SDC quality check.

Requirements

1. Synthesize experience by DC / DC‑NXT / Fusion‑Compiler.

2. EQV debug experience by FM / LEC.

3. Low power check experience by VC‑LP.

4. Static Timing Analysis experience by PT.

5. Power Analysis experience by PTPX.

6. Good at scripts, like Python / perl / Tcl / Shell.

7. Language proficiency : Mandarin and English.

Responsibilities

The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on‑chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring‑up and also support post‑silicon debug.

1. Interfacing with the design teams to ensure DFT design rules and guidelines are met.

2. Interact with PD and Front End Integration team for Scan Insertion.

3. Generating high quality manufacturing test patterns for stuck‑at, transition fault models and CA Model.

4. Simulating and verifying the ATPG and LBIST patterns.

5. Working with the product engineering teams on the delivery of manufacturing test patterns.

6. Developing, enhancing and maintaining scripts as necessary.

7. Able to technically guide and mentor junior folks in the team.

Requirements

Bachelors or Masters degree in computer engineering / Electrical Engineering.

Prior experience as DFT engineer.

1. Experience in creating and implementing complex chip‑level DFT architecture.

2. Experience in DFT implementation including Scan insertion, ATPG and Simulations.

3. Experience with DFT tools, ATPG (Stuck‑At, At‑Speed, Path‑Delay) and scan compression.

4. Experience in debugging low coverage and DRC fixes.

5. Experience of debugging test pattern issues.

6. Support the Silicon bringup activities to guarantee highest stability of the test pattern.

7. Knowledge of MBIST is a plus.

8. Knowledge of synthesis is a plus.

9. Experience with post‑silicon debug.

10. Comfortable in Linux environment and writing / using scripting languages such as Perl, Tcl, etc.

11. Any Tessent Scan / ATPG certifications is a plus.

12. Excellent presentation and inter‑communication skills.

Responsibilities

1. Responsible for digital circuit back‑end design, completing the full digital APR (Automatic Place and Route) flow from netlist to GDS, including floorplanning, clock tree synthesis (CTS), placement, routing, and final GDS generation; experience with top‑level design is preferred.

2. Perform physical verification such as DRC and LVS on the GDS output to ensure design integrity.

3. Communicate effectively with design engineers to fully understand design requirements and resolve technical challenges during the design process.

4. Participate in developing IC‑related technical documentation and preparing design reports.

Requirements

1. Bachelor’s degree or above, with at least 2 years of experience in digital APR; experience in top‑level or subsystem design is preferred.

2. Major in Microelectronics, Computer Science, or Electronic Engineering.

3. Proficient with back‑end design tools such as Innovus, Calibre, StarRC / QRC, PrimeTime (PT), Redhawk, and Virtuoso.

4. Solid understanding of integrated circuit process and design fundamentals; with strong logical and analytical skills; experience in advanced process node technologies is a plus.

5. Responsible, proactive, and detail‑oriented, with strong teamwork and communication skills.

Responsibilities

1. Post‑silicon bring‑up and validation of internal IPs on complex SoC platforms.

2. Collaborate with architecture, design, and firmware teams to understand IP specifications and

3. Develop and execute test plans for functional validation of peripheral IPs (e.g., PCIe, USB, eSPI, I2C, I3C).

4. Debug and resolve silicon and system‑level issues through hands‑on lab work and analysis.

5. Document validation results, findings, and recommendations for design and system improvements.

Requirements

1. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

2. Strong understanding of computer architecture and high‑speed peripheral protocols.

3. Hands‑on experience with post‑silicon validation, lab equipment, and debug tools.

4. Familiarity with SoC system integration and low‑level firmware interaction is a plus.

5. Excellent problem‑solving skills and ability to work in a collaborative environment.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Semiconductor Manufacturing

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