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Senior Design Verification Engineer
UST Global (M) Sdn BhdPenangMalaysia, Penang, Malaysia20 jam yang lalu
Penerangan pekerjaanExperience of digital IP verification with SV / UVM / Formal Verification or new methodology in industry. Good understanding of ASIC verification concepts and techniques, Verilog / SystemVerilog, and UVM. Good at scripting languages such as Perl, Python; or database experience for IP technical info maintenance. Over 2 years’ experience focusing on SV assertion / coverage / formal verification. Bachelor’s degree or higher in Electrical and Electronics Engineering or related field. 4-6 years of relevant experience. What's your expected monthly basic salary? How many years' experience do you have as a Design Verification Engineer?
About the Role
Will be part of a team that handles Verification for complex IPs and close the Verification to the challenging milestones.
Responsibilities
- IP verification : VR creation as per chip requirements and UVM / OVM test bench creation.
- Support building verification infrastructure at chip level as per requirements.
- Handle multiple areas of IP verification : RTL, Power Aware, and Gate Level Verification.
- Collaborate with team and functional leads; interact with cross‑functional groups.
Job Requirements
Application Questions
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Design Engineer • PenangMalaysia, Penang, Malaysia