IP Design Architect

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IP Design Architect

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IP Design Architect

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Altera Get AI-powered advice on this job and more exclusive features. Develops and drives end-to-end architecture for highly optimized, modular, and scalable FPGAs and FPGA SoC products. Performs top-down architectural analysis of FPGA core components such as programmable logic, routing, DSP units, memory banks, reconfigurable clocking, and configuration subsystems. Ensures and supports interoperability of hardware and software throughout the product life cycle. Creates and reviews functional and design specifications for FPGA subsystems and provides trade-off analysis and design options based on hardware and system features, IP integration and fabric requirements, interoperability of hardware and software, and regulatory and compliance requirements. Invents, conceptualizes, and specifies microarchitecture and architectural features to deliver optimized FPGA solutions for high-performance and power-optimized products. Develops testing approach and preliminary test plans for new architectures / features for FPGA, performs functional modeling simulations, gate-level simulations, and conducts analysis of test results using advanced statistics and data predictions for benchmarking performance and determining areas for improvement. Provides experimental / proof-of-concept changes for proposing design alternatives meeting performance, power, area, and timing constraints. Reviews, challenges, and influences cross-functional roadmaps, and defines technology targets for future FPGA solutions. Collaborates with architects as well as design, system, verification, and manufacturing engineers to improve the overall design for FPGA and overcome constraints.

Job Details

Job Description :

Develops and drives end-to-end architecture for highly optimized, modular, and scalable FPGAs and FPGA SoC products. Performs top-down architectural analysis of FPGA core components such as programmable logic, routing, DSP units, memory banks, reconfigurable clocking, and configuration subsystems. Ensures and supports interoperability of hardware and software throughout the product life cycle. Creates and reviews functional and design specifications for FPGA subsystems and provides trade-off analysis and design options based on hardware and system features, IP integration and fabric requirements, interoperability of hardware and software, and regulatory and compliance requirements. Invents, conceptualizes, and specifies microarchitecture and architectural features to deliver optimized FPGA solutions for high-performance and power-optimized products. Develops testing approach and preliminary test plans for new architectures / features for FPGA, performs functional modeling simulations, gate-level simulations, and conducts analysis of test results using advanced statistics and data predictions for benchmarking performance and determining areas for improvement. Provides experimental / proof-of-concept changes for proposing design alternatives meeting performance, power, area, and timing constraints. Reviews, challenges, and influences cross-functional roadmaps, and defines technology targets for future FPGA solutions. Collaborates with architects as well as design, system, verification, and manufacturing engineers to improve the overall design for FPGA and overcome constraints.

Qualifications

Education Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (Bachelor’s with extensive experience is also acceptable). Strong academic background in VLSI, Computer Architecture, and Digital Design. Technical Skills

FPGA Architecture & System-Level Expertise

Strong knowledge of FPGA architectures Experience defining scalable and reusable IP architectures for FPGA-based designs. Deep understanding of clocking, reset strategies, and multi-clock domain designs. Experience with low-latency, high-throughput, and power-efficient architectures.

RTL Design & FPGA Development

Expertise in Verilog / SystemVerilog and VHDL for FPGA-based IP development. Experience with FPGA-optimized microarchitecture design, including pipelining, state machines, and parallel processing. Strong knowledge of floating-point and fixed-point arithmetic, DSP algorithms, and hardware acceleration.

FPGA IP Integration & High-Speed Interfaces

Deep understanding of high-speed serial interfaces (PCIe, Ethernet, JESD204, CPRI, ORAN and etc). Experience with memory interfaces (DDR4, HBM, LPDDR, GDDR) and FPGA memory controllers. Strong knowledge of AMBA protocols (AXI, AHB, APB) and custom bus architectures.

Synthesis, Timing, and Hardware Optimization

Expertise in FPGA synthesis, place & route, and static timing analysis (STA). Experience optimizing Power, Performance, and Area (PPA) trade-offs in FPGA designs. Knowledge of HLS (High-Level Synthesis) for FPGA-accelerated designs

Simulation, Verification & Debugging

Experience with simulation tools Knowledge of formal verification, assertion-based verification (SVA), and FPGA debugging tools (ILA, SignalTap, Chipscope).

Scripting & Automation

Proficiency in Python, TCL, or Perl for FPGA design flow automation. Experience with Linux shell scripting and FPGA build automation. Experience & Industry Knowledge 10+ years of experience in FPGA / ASIC design, development, or architecture. Experience working with military, aerospace, automotive, or data center FPGA applications is a plus. Familiarity with HPC, AI / ML acceleration, or software-defined radio (SDR) architectures is beneficial. Knowledge of safety-critical design standards (DO-254, ISO 26262, or IEC 61508) is a plus. Soft Skills & Leadership Technical Leadership : Ability to mentor engineers, review designs, and define FPGA IP strategies. Problem-Solving : Strong debugging skills for FPGA timing, functionality, and performance issues. Communication : Ability to document and present FPGA IP architectures to internal teams and customers. Collaboration : Experience working with software, verification, and hardware teams.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location :

Penang 15, Penang, Malaysia

Additional Locations :

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Seniority level

Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

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