Package Design Engineer

Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies

Key Responsibilities

• Perform the design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
• Perform package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
• Ensure designs comply with substrate manufacturing rules (trace width / spacing, via design, impedance requirements).
• Incorporate assembly rules (die placement, bump / ball pitch, solder joint reliability, warpage control) into package designs.
• Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations.
• Collaborate with Signal Integrity (SI), Power Integrity (PI), and thermal analysis teams to ensure robust performance.
• Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility.
• Provide on-site vendor support when required to resolve design and assembly issues.

Skills & Qualifications

Seniority level : Mid-Senior level

Employment type : Full-time

Job function : IT Services and IT Consulting

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