(JO) Senior Layout and Physical Design Engineer (58373)

We are seeking analog / mixed-signal IP layout and physical design to lead layout implementation, RTL-to-GDSII execution and mentor juniors while working with top EDA tools. Be part of a team building high-performance semiconductor solutions.

Job Description :

• Independently execute layout of analog / mixed-signal IP blocks (e.g., ADCs, LDOs, PLLs, bandgaps, IOs)
• Work closely with logic and circuit designers to meet performance, area, and matching constraints
• Support top-level floorplanning and layout integration
• Perform DRC / LVS / PEX and support sign-off processes
• Participate in technical reviews and contribute to best practices in layout & physical design methodology
• Block execution of physical design, including synthesis, Place and Route and Design and Timing Closure
• Lead and guide junior engineers on the block execution (Apply now at #J-18808-Ljbffr