Design Verification Engineer

USTBayan Lepas, Penang, Malaysia

30+ days ago

Job description

We are hiring Engineers! | Talent Acquisition @ UST

(Multiple headcounts available in different specializations)

UVM & SV

Job Responsibilities :

Be part of a team verifying complex IPs and driving them to closure against challenging milestones.

Build verification environments and UVM / OVM testbenches based on chip requirements.

Work across RTL, power-aware, and gate-level verification.

What we’re looking for :

Bachelor’s degree (or higher) in Electrical / Electronic Engineering or related.

3–4+ years of hands‑on experience in digital IP verification using SV / UVM or similar methodologies.

Solid knowledge of ASIC verification concepts.

Bonus if you’ve dabbled in scripting (Perl / Python) or have database know‑how.

Willing to relocate and work in Penang, Malaysia

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Industries

IT Services and IT Consulting

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Design Engineer • Bayan Lepas, Penang, Malaysia

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