VLSI CAD / EDA Engineer — RTL & Verification

A leading semiconductor company in Penang, Malaysia, is seeking an experienced CAD / EDA Engineer to contribute to the development of logic design methodologies. The ideal candidate will have 3 to 5 years of EDA experience and a solid understanding of Verilog, with a focus on CDC and logic verification. This role involves collaboration across teams and continuous improvement initiatives in a dynamic environment.

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