Design Eng 3

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills

We are looking for a passionate digital design engineer to build a High Speed Serial Protocol Hard-IP portfolio for Lattice FPGA. The individual should have the ability to work closely with Principal Engineer or Architect to translate specifications into RTL design, ensuring the best performance, low power consumption, and optimal logic utilization. Accountabilities / Exposure : Own unit level design and IP integration. Own design quality checks with exposure to industry-standard EDA tools and methodologies. Define design timing constraints and ensure timing convergence. Plan open-box testing, write assertion checks, and debug. Perform code coverage analysis and work towards closure. Support silicon power-on and post-silicon validation. Develop new design methodologies. Automate design flow tasks through scripting. Create design documentation, e.g., micro-architecture and implementation documents. Qualifications : Good understanding of ASIC / FPGA IP or SoC development cycles. Knowledge of High-Speed Serial Protocols such as Ethernet, PCIe, MIPI, or Universal Transceiver. Proficiency in RTL design with Verilog or SystemVerilog and design constraints. Experience with design quality check methodologies, e.g., Lint, CDC, RDC, Fishtail, or UPF flow. Advanced user of logic simulation EDA tools like Cadence Xcelium, Synopsys VCS, or Siemens Questa. Experience collaborating with Design Verification teams on test plans, assertion coding, coverage analysis, and debugging. Familiarity with Physical Design processes like Synthesis, LEC, or Timing Closure. Programming skills in Perl, Shell Scripting, TCL, Java, Python, or C / C++, and familiarity with Linux OS. Experience in technical writing, including micro-architecture documentation, publications, or patents. Self-motivated with strong communication skills, promoting innovation and teamwork. Experience in silicon power-on or hardware validation is a plus. Experience in team supervision or leading design delivery is a plus.

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