Exposure in Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM / IR
Extensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
Hands on experience on 16nm, 14nm, 12nm, and sub-10nm projects
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
Job Requirements
At least 4 years of relevant experience
Experience in FinFET & Dual Patterning nodes such as 16 / 14 / 12 and sub-10nm nodes
Excellent physical design and timing background
Strong analytical / problem solving skills and pronounced attention to details
Seniority level
Mid-Senior level
Employment type
Full-time
Industry
Semiconductor Manufacturing
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