Physical Design Engineer

Direct message the job poster from ThunderSoft

We are seeking an adaptive, self‑motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive capabilities in delivering high‑performance, power‑efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible full‑chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs.

THE PERSON :

You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full‑chip floorplanning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem‑solving abilities, are eager to learn, and thrive in tackling complex design challenges.

Key Responsibilities

• Extensive hands‑on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification
• Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus
• Solid understanding of low‑power design methodologies, including power‑aware synthesis and place‑and‑route; familiarity with voltage domain checks is advantageous
• Proven experience in chip‑level floorplanning, including feedthrough topology planning, repeater insertion, and top‑level port / pin assignment
• Tapeout experience across multiple projects

Preferred Experience

Academic Credentials

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