Senior Physical Design Engineer

Hiring Top Semiconductor Engineers across APAC Region and Vietnam | Connecting Talents to Opportunities | Talents Strategist | Follow me for more Job…

Education : B.Tech / BE / ME / M.Tech

Experience : 6+ years

Responsible for all aspects of Physical design (Place & Route, STA analysis, PI / SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies. The candidate should be able to drive the project and guide team members along with his own responsibilities / tasks.

Requirements

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floorplanning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl / Perl / Shell / Python programming, Mentor Calibre DRC / LVS / PERC, and Apache Totem EM & IR analysis is a plus.
• Participate and contribute in enhancing physical design methodologies and flows.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog / custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment

Working time

Monday - Friday

Benefits

Health insurance, flight ticket, work visa

Contact

Ms. Van Anh – Whatsapp :

Email :

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering Services and Semiconductor Manufacturing

#J-18808-Ljbffr