System Validation Engineer

Overview

We are looking for a dynamic, energetic Systems Validation Engineer to join our growing team. You will work on the development of methodologies, execution of system integration / System plans, and debugging of failures. You will collaborate with Architecture, Design, and Pre-silicon integration teams to improve post-silicon test content and provide feedback for future debug and test features. You will use and apply platform level tools and techniques to ensure silicon quality.

The Person :

As a Systems Validation Engineer, you will deliver our next generation of system validation tests for our products. In this high visibility position, your systems engineering expertise will be necessary to find and resolve silicon platform issues.

Responsibilities

• Work with global teams closely to define test strategy, develop a smart system validation plan on post-silicon level, and provide fast responses for issue debug.
• Collaborate with functional teams and drive end-to-end work from planning to execution and issue debug.
• Deliver professional project reports to management, highlight risks in a timely manner with solution plans.
• Improve system level integration / system level test strategies, methodologies, and processes.
• Collaborate with multi-functional hardware and software teams to debug and tackle complex issues.
• Develop and improve automation features according to requirements.

Preferred Experience

Academic Credentials

Seniority level

Employment type

Job function

Industries

We are committed to equal employment opportunity. Referrals may increase your chances of interviewing at UST Malaysia.

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