Assistant Manager - Regional Recruitment at TG Malaysia | APAC Talent Acquisition Leader | Driving Cross-Border Hiring Strategies
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Job Description :
- Participate in block / IP / chip floor planning from scratch, performing routing & layout verification (such as LVS, DRC, Antenna & others) and troubleshooting the results
- Co-lead / lead the physical layout of IP / full chip design by working closely with cross functional team leader (Teresa : requirements for Senior Staff / Staff Engineer level)
- Conduct thorough layout design reviews internally & external review with circuit designers
- Extensive use of CAD tools (Cadence Virtuoso VXL & Mentor Calibre) in IP / chip integration and verification
- Capable in guiding / coaching junior engineers for on time delivery & quality
Job Requirements :
Bachelor’s degree in electrical / Electronic Engineering / Physics with VLSI exposure or equivalent 9 to 14 years of job experience in layout design field is preferred.Hands on with Analog Layout, Layout Versus Schematic, +Cadence Virtuoso, CMOS, Analog CMOS Circuits, Floorplanning, Layout Verification, Design Rule Checking, VLSI DesignHands‑on experience in analog layout from scratch, implementation of analog layout techniques, IR drop / EM analysisDeep understanding of analog circuit layout concepts in submicron CMOS technologiesPossess strong technical, analytical & problem‑solving skills in layout designSeniority level
Mid-Senior level
Employment type
Full-time
Job function
Information Technology, Engineering, and Design
Industries
Semiconductor Manufacturing
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Georgetown, Penang, Malaysia
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