Direct message the job poster from UST Malaysia
Job Title
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Experience : 4-8 years
Education : Bachelors or Masters degree in computer engineering / Electrical Engineering.
We are seeking a highly skilled Physical Design Engineer with strong expertise in ASIC / SoC physical design, synthesis, and engineering change order (ECO) implementation. The ideal candidate will work closely with RTL design, verification, and backend teams to deliver high-quality silicon designs while meeting timing, area, and power goals.
Responsibilities
- Perform RTL synthesis and optimize design to meet timing, area, and power targets using industry-standard synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).
- Implement ECO changes efficiently during the design closure phases to fix timing or functionality issues without full re-synthesis.
- Collaborate with backend physical design teams to ensure smooth handoff from synthesis to place-and-route stages.
- Analyze timing reports, constraints, and implement fixes to meet design specifications.
- Support the physical design flow including clock tree synthesis, placement, routing, and timing closure.
- Work with signoff teams for static timing analysis (STA) and design for test (DFT).
- Develop scripts and automation flows to improve productivity and reduce turnaround time.
- Participate in design reviews and provide technical inputs related to synthesis and ECO methodologies.
- Stay current with industry trends and best practices in physical design and synthesis.
Qualifications
Bachelor’s / Master’s degree in Electrical Engineering, Computer Engineering, or related field.Strong experience with RTL synthesis tools such as Synopsys Design Compiler or Cadence Genus.Expertise in ECO implementation techniques including patch ECO, synthesis ECO, and netlist modifications.Solid understanding of ASIC physical design flow and constraints.Proficient in scripting languages like Tcl, Perl, or Python for flow automation.Experience with STA tools (PrimeTime or equivalent).Good knowledge of timing analysis, clock tree synthesis, and low-power design techniques.Ability to troubleshoot and debug design issues effectively.Excellent teamwork and communication skills.Preferred
Experience with industry-standard P&R tools (e.g., Synopsys ICC2, Cadence Innovus).Familiarity with DFT and design for manufacturability (DFM).Knowledge of power optimization and multi-voltage domain designs.Experience working in agile design environments.Contact
Ms. Anna - WhatsApp :
Email :
Seniority level
Mid-Senior levelEmployment type
Full-timeNote : This description focuses on the responsibilities, qualifications, and contact details related to the Physical Design Engineer role at UST Malaysia. Other job postings and extraneous content have been removed to improve clarity.
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